Systems and methods for forming die sets with die-to-die routing and metallic seals

ABSTRACT

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/801,163 filed on Nov. 1, 2017, which claims the benefit of priorityfrom U.S. Provisional Patent Application Ser. No. 62/484,330 filed onApr. 11, 2017, both of which are incorporated herein by reference.

BACKGROUND Field

Embodiments described herein relate to integrated circuit (IC)manufacture, and the interconnection of multiple die.

Background Information

Microelectronic fabrication of ICs is typically performed using asequence of deposition and patterning of circuit elements in alayer-by-layer sequence in which a stepper (or scanner) is used to passlight through a reticle, forming an image of the reticle pattern on anunderlying layer. Rather than expose an entire wafer, the stepper movesin steps across the wafer from one die area location to another. In thismanner, working on a limited area enables higher resolution and criticaldimensions.

Current high end steppers or scanner systems are 4× or 5× reductionsystems. Thus, the reticle features are 4 or 5 times the size of thefeature to be formed on the wafer. Furthermore, one known standard sizeof reticles is approximately a 5 inch (127 mm) plate. At 4×, thiscorresponds to an approximately 32 mm field size at the wafer level.Thus, depending upon the manufacturer and equipment, 32 mm may beconsidered an exemplary upper limit on die size lateral dimension.

A multi-chip module (MCM) is generally an electronic assembly in whichmultiple die are integrated on a substrate. Various implementations ofMCMs include 2D, 2.5D and 3D packaging. Generally, 2D packaging modulesinclude multiple die arranged side-by-side on a package substrate. In2.5D packaging technologies multiple die and bonded to an interposerwith microbumps. The interposer in turn is then bonded to a packagesubstrate. The interposer may include routing to interconnect theadjacent die. Thus, the die in 2.5D packaging can be directly connectedto the interposer, and are connected with each other through routingwithin the interposer. Generally, 3D packaging modules include multipledie stacked vertically on top of each other. Thus, the die in 3Dpackaging can be directly connected to each other, with the bottom diedirectly connected to a package substrate. The top die in a 3D packagecan be connected to the package substrate using a variety ofconfigurations, including wire bonds, and through-silicon vias (TSVs)though the bottom die.

SUMMARY

Stitched die structures and methods of interconnecting die are describedin which adjacent die are interconnected with a die-to-die routingformed within a back-end-of-the line (BEOL) build-up structure thatspans over adjacent die areas on a semiconductor substrate. Thedie-to-die routing in accordance with embodiments may be formed of avariety of layers, including pre-formed die routing within the die areas(e.g. formed using the die area reticles), stitch routing (e.g. formedwith stitching tools), and layers within multiple levels of the BEOLbuild-up structure. Furthermore, the die-to-die routing may be formedusing multiple layers with different design rules (e.g. line width, linethickness, line spacing, line pitch, etc.). Embodiments may be used tointerconnect a variety of die together such as, but not limited to, dieincluding functionality such as graphics processing units (GPUs) and acentral processing units (CPUs). Additionally, high densityinterconnects can be formed at chip-like density and cost, withflexibility to scribe out good clusters, which can vary from single dieto a large number of die on a wafer.

In one implementation, the metallic seals and die-to-die routing arepre-formed during formation of the BEOL build-up structure. The die maythen be tested to bin the die into clusters, followed by dicing of diesets within stitched die structures. In another implementation, themetallic seals are not pre-formed. In such an embodiment, the formationof die-to-die routing and selection of scribe/dicing areas is customizedaround each die. In accordance with embodiments, the stitched diestructures described may be mounted on a module substrate along with anyother module chips and surrounded by a hermetic seal, which can providean additional layer of protection to the metallic seal(s), or facilitaterelaxing some of the on-chip seal and/or keep out zone requirements ofthe stitched die structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional side view illustration of astitched die structure in accordance with an embodiment.

FIG. 2A is a schematic top view illustration of a wafer including anarray of die areas in accordance with an embodiment in which adjacentdie are interconnected with die-to-die routing extending throughmetallic seals.

FIGS. 2B-2C are schematic top view illustrations of die areas withinreticle patterns in accordance with embodiments.

FIG. 2D is a flow chart of a method of forming a stitched die structurewith pre-formed metallic seal in accordance with embodiments.

FIG. 3 is a schematic illustration of a pre-formed routing extendingthrough a metallic seal in accordance with an embodiment.

FIG. 4A is a schematic illustration of a multiple level pre-formedrouting extending through a metallic seal in accordance with anembodiment.

FIG. 4B is a schematic side view illustration taken along upper levelsection B of FIG. 4A in accordance with an embodiment.

FIG. 4C is a schematic side view illustration taken along lower levelsection C of FIG. 4A in accordance with an embodiment.

FIG. 4D is a schematic cross-sectional side view illustration ofpartially diced dies with additional passivation in accordance with anembodiment.

FIG. 5 is a schematic illustration of a portion of die-to-die routingincluding stitch routing connected to routing that extends through ametallic seal accordance with an embodiment.

FIG. 6A is a circuit diagram for two connected dies in accordance withan embodiment.

FIG. 6B is a circuit diagram for two diced dies in accordance with anembodiment.

FIG. 7A is a detection circuit diagram for a connected die routingsaccordance with an embodiment.

FIG. 7B is a detection circuit diagram for unconnected die routings inaccordance with an embodiment.

FIG. 8A is a schematic top view illustration of a wafer including anarray of die areas in accordance with an embodiment in which a metallicseal is formed around adjacent die that are interconnected withdie-to-die routing.

FIG. 8B is a flow chart of a method of forming a stitched die structurewith a custom metallic seal in accordance with embodiments.

FIG. 9 is a schematic top view illustration of a probing arrangement ona wafer supporting an array of dies in accordance with an embodiment.

FIG. 10 is a schematic illustration of a die-to-die input/output circuitincluding digital and analog components in accordance with anembodiment.

FIG. 11A is a schematic illustration of a die I/O connectionconfiguration with an unused spare I/O circuit in accordance with anembodiment.

FIG. 11B is a schematic illustration of a die I/O connectionconfiguration with a connected spare I/O circuit in accordance with anembodiment.

FIG. 12A is a schematic top view illustration of a module including astitched die structure in accordance with an embodiment.

FIGS. 12B-12E are schematic top view illustrations stitched diestructures including metallic seals around active areas in accordancewith embodiments.

DETAILED DESCRIPTION

Embodiments describe stitched die structures, and methods forinterconnecting die. Specifically, embodiments utilize die stitchingtools to interconnect die while at the wafer level, followed by carvingout multiple die sets during dicing. In one aspect, die stitching mayfacilitate the use of smaller tiles, or die areas, which can lead tobetter yielding. For example, smaller die areas may result in lessdefects per die, higher wafer utilization (die per wafer), and allowingchip scaling (e.g. 1 core . . . n core). In another aspect, diestitching in accordance with embodiments can be utilized to fabricatedie sets that are larger than a single reticle size.

In another aspect, the stitched die structures may facilitate theformation of high density die-to-die interconnects at a chip likedensity, using line and spacing dimensions utilized in BEOL processing.Additionally, the stitched die structures preserve the ability to bedirectly connected to a packaging substrate or circuit board. Thestitched die structures in accordance with embodiments, may allow forreduced input/output (I/O) area (e.g. including bond pads), and improvedelectrical characteristics (e.g. power requirements, capacitance), andreduced latency commonly associated with existing packaging solutions.For example, microbumping pitch (e.g. die to interposer) commonly foundin 2.5D packaging solutions is commonly in the tens of microns. Inaccordance with embodiments, on-chip metal/via pitch can be sub-micron.In accordance with embodiments, the I/O area and beachfront may be onthe order of a magnitude less than traditional solutions.

In accordance with embodiments, multiple die are stitched together whenforming the back-end-of-the-line (BEOL) build-up structure over multipledie at the wafer scale. In an embodiment, a stitched die structureincludes multiple die with the same functionality, such as a graphicsprocessing unit (GPU) or central processing unit (CPU). Thus, anexemplary stitched die structure may include a multiple GPU die stitchedtogether, or multiple CPU die stitched together, though embodiments arenot limited to these specific ICs.

In accordance with embodiments, the stitched die structures include oneor more metallic seals around a peripheral area of the die. For example,the metallic seals may provide physical protection (e.g. fromenvironment (e.g. moisture), stress, micro-cracks) and/or electricalprotection (e.g. electromagnetic interference, electrostatic discharge).In some embodiments, the die-to-die routing is formed through themetallic seals of each die in the stitched die structure. In otherembodiments, the metallic seals are selectively formed around groups ofdie in the stitched die structures, where die-to-die routing is formedinside the metallic seal perimeter. In application, modules includingthe stitched die structure and any other chips can be hermiticallysealed. This adds additional protection to the seal rings. For example,moisture (or other environmental factor) has to navigate through thehermetic barrier first, and the metallic seal is an added layer ofprotection. This may be particularly applicable for high reliabilitysystems. Alternatively, the metallic seals may facilitate relaxing someof the on-chip seal and/or keep out zone requirements for cost-sensitivesystems.

In various embodiments, description is made with reference to figures.However, certain embodiments may be practiced without one or more ofthese specific details, or in combination with other known methods andconfigurations. In the following description, numerous specific detailsare set forth, such as specific configurations, dimensions andprocesses, etc., in order to provide a thorough understanding of theembodiments. In other instances, well-known semiconductor processes andmanufacturing techniques have not been described in particular detail inorder to not unnecessarily obscure the embodiments. Reference throughoutthis specification to “one embodiment” means that a particular feature,structure, configuration, or characteristic described in connection withthe embodiment is included in at least one embodiment. Thus, theappearances of the phrase “in one embodiment” in various placesthroughout this specification are not necessarily referring to the sameembodiment. Furthermore, the particular features, structures,configurations, or characteristics may be combined in any suitablemanner in one or more embodiments.

The terms “above”, “over”, “to”, “between”, “spanning” and “on” as usedherein may refer to a relative position of one layer with respect toother layers. One layer “above”, “over”, “spanning” or “on” anotherlayer or connected “to” or in “contact” with another layer may bedirectly in contact with the other layer or may have one or moreintervening layers. One layer “between” layers may be directly incontact with the layers or may have one or more intervening layers.

Referring now to FIG. 1 a schematic cross-sectional side viewillustration is provided of a stitched die structure 100 in accordancewith an embodiment. As shown, a stitched die structure 100 may include asemiconductor substrate 101 including a first die area 110A of a firstdie 104A and a second die area 110B of a second die 104B separate fromthe first die area 110A. A back-end-of-the-line (BEOL) build-upstructure 120 spans over the first die area 110A and the second die area110B. In an embodiment, the BEOL build-up structure 120 includes a firstmetallic seal 122A directly over a first peripheral area of the firstdie area 110A, a second metallic seal 122B directly over a secondperipheral area of the second die area 110B. For example, the first andsecond metallic seals 122A, 122B may be seal rings. The BEOL build-upstructure 120 additionally includes die-to-die routing 130 that extendsthrough the first metallic seal 122A and second metallic seal 122B toelectrically connect the first die 104A to the second die 104B. The BEOLbuild-up structure 120 may additionally include a plurality of contactpads 140 such as, but not limited to, under bump metallurgy pads, whichmay be electrically connected to the first and second die 104A, 104B,and optionally the metallic seals 122A, 122B.

Still referring to FIG. 1, the die-to-die routing 130 may include dierouting 135 from each die connected with stitch routing 136. Inaccordance with embodiments, the die routing 135 may be formed from oneor more vias 132 and metal layers 134 within the BEOL build-up structure120. In the particular embodiment illustrated, the die-to-die routing130 includes multiple routings, formed within multiple metal layers. Inaccordance with embodiments, the die-to-die routing 130 can be formedwithin the lower metal layers M_low, upper metal layers M_high, midlevelmetal layers M_mid, and combinations thereof. Generally, the lower metallayers M_low have finer line widths and spacing. This may be attributedto making connections between devices. The upper metal layers M_high mayhave coarser line widths and line spacing, with the midlevel metallayers M_mid having intermediate line widths and spacing.

FIG. 2A is a schematic top view illustration of a wafer 102 including anarray of die areas 110 in accordance with an embodiment in whichadjacent die are interconnected with die-to-die routing 130 extendingthrough metallic seals 122. As illustrated, the metallic seals 122 maybe formed directly over peripheries of the die areas 110. In accordancewith embodiments, portions of the die-to-die routing 130 may bepre-formed through the metallic seals 122 in each die area 110. FIG. 2Ais an illustration of an embodiment, in which some of the adjacent dieillustrated with shading are connected with die-to-die routing.Specifically, the die-to-die routing 130 may include a first die routing135 formed through a first metallic seal 122, and a second die routing135 formed through a second metallic seal 122. The first and second dieroutings 135 may be pre-formed in each die area 110. Die routings 135may be formed of the metal layers 134 and optionally vias 132 within theBEOL build-up structure 120. As shown in the close-up illustration, thedie-to-die routing 130 additionally includes stitch routing 136 thatphysically and electrically connects the first and second die routings135 of adjacent die, and more specifically metal layers 134 of therespective die routings 135.

In an embodiment, the formation of pre-formed die-to-die routing 130 andmetallic seals 122 as illustrated in FIG. 2A may facilitate the abilityto dynamically scribe out good die sets that have been identified asgood die after testing. Thus, scribing can be dynamically adjusted perwafer 102 since passing and failing clusters may change for each wafer.Additionally, the formation of pre-formed metallic seals 122 anddie-to-die routings 130 may facilitate the ability to dynamically changethe number of die 104 to be included in each stitched die structure 100.While the exemplary stitched die structure 100 illustrated in FIG. 2Aincludes two die 104 (illustrated by die areas 110), embodiments are notlimited and any number of die 104 may be included, such as three, four,etc. and may be stitched together at different sides. For example,die-to-die routing 130 may be pre-formed at any or all sides of the dieareas 110 to allow for dynamic grouping of die sets within the stitcheddie structures 100.

FIGS. 2B-2C are schematic top view illustrations of die areas withinreticle patterns in accordance with embodiments. In the exemplaryembodiment illustrated in FIG. 2B multiple die areas 110 fit inside asingle reticle area 111. For example, each die area 110A-110D may be asame die 104 (e.g. GPU, CPA) or the multiple die areas 110A-11D mayinclude multiple different dies 104. In the embodiment illustrated inFIG. 2B a single reticle pattern includes multiple die areas 110. Asdescribed in further detail below, any or all of the die areas 110 mayinclude die-to-die input/output circuits 108A interconnected withdie-to-die routing 130. Die routings 135 may additionally extend fromone or more die areas 110A-D for potential connection with an adjacentdie of an adjacent reticle area 111. In an embodiment, adjacent die 110with a single reticle pattern 111 can be connected with die-to-dierouting 130 which may include only die routings 135, or alternatively acombination of die routings 135 and stitch routing 136, or both. Forexample, some die areas 110 may be connected with die routings 135 only,while others are connected with a combination of die routings 135 andstitch routing 136. In the embodiment illustrated in FIG. 2C, a singlereticle pattern includes a single die area 110. Adjacent die areas 110of adjacent reticle areas 111 may be the same or different types ofdies. In an embodiment, die-to-die routing 130 between adjacent dieareas 110 of adjacent reticle areas 111 is connected with a combinationof die routings 135 and stitch routing 136.

Referring now to FIG. 2D, a flow chart is provided of a method offorming a stitched die structure 100 with pre-formed metallic seal inaccordance with embodiments. At operation 2010 a BEOL build-up structure120 is formed over the wafer 102 including pre-formed die-to-die routing130 and metallic seals 122 for each die area 110. The individual die 104are then tested at operation 2020. Testing may be performed at waferlevel and may be performed using non-contact circuit probes (e.g. radiofrequency) or contacting circuit probes with contact pads. In accordancewith embodiments, testing may be used to bin the die into groups, forexample, to identify good and bad die clusters. Die sets within goodclusters may then be dynamically scribed out into specified stitched diestructures 100 at operation 2030. As shown in FIG. 2A scribing may beaccompanied by cutting through stitch routing 136, or optionally dierouting 135, or both. However, since this cut portion of the die-to-dierouting 130 will not be used, this may not affect performance of thestitched die structure 100. Following dicing the die sets may bepackaged, followed by a final package level test of the die sets.

FIG. 3 is a schematic illustration of a pre-formed die routing 135extending through a metallic seal 122 in accordance with an embodiment.The schematic illustration in FIG. 3 illustrates a dicing area 150between two adjacent die areas 110 on a wafer 102. As shown by thearrows, in a direction starting from a diced die 104 edge illustrated bythe dotted line, each die 104 includes a metallic seal 122 which maysurround an active area 108 including die-to-die input/output circuits108A and core logic circuits 108B located more centrally inside the diearea 110. For example, sensitive circuits such as SRAM may be locatedcentrally within the die area 110, and separated from the die-to-dieinput/output circuits 108A by a keep out zone (KOZ).

In accordance with embodiments, the pre-formed die routing 135 thatextends through the metallic seal 122 may terminate prior to, or extendpast, the pre-determined edge of the die area 110 that results fromdicing. Thus, when adjacent die 104 are diced, the terminal ends of thepre-formed die routing 135 or stitch routing is not connected to anadjacent die.

Die routing 135 may be formed through the metallic seals 122 in avariety of configurations. In many embodiments, the die routing 135 isformed through the metallic seals 122 (e.g. seal rings) to prevent aclear line of sight. This may be accomplished using single level dierouting 135 (e.g. within a single metal layer in the BEOL build-upstructure), multiple level die routing 135 (e.g. within multiple metallayers in the BEOL build-up structure), and through formation the dierouting 135 through multiple metallic seals 122. In the embodimentillustrated in FIG. 3, the pre-formed die routing 135 extends through anopening 124 in the metallic seal 122. Like the die routing 135, theopening 124 may be a single level or multiple level opening. In anembodiment, the die routing 135 illustrated in FIG. 3 may be considereda single level routing formed through a single level opening 124. Stillreferring to FIG. 3, as illustrated, multiple die routings 135 may beformed through a single opening 124 in the metallic seal 122.Additionally, multiple openings 124 and die routings 135 may be formedwithin a single level of the BEOL build-up structure. Referring back toFIG. 1, in accordance with embodiments, multiple die routings 135 may beformed through multiple openings 124 in multiple levels of the BEOLbuild-up structure. Furthermore, the die routings 135 within differentlevels may be formed with different, or the same, rules for line widthsand spacing.

Referring now to FIG. 4A, a schematic illustration is provided of aportion of multiple level pre-formed die routing 135 extending through ametallic seal 122 in accordance with an embodiment. FIG. 4A issubstantially similar to FIG. 3, with one difference being the multiplelevel die routing 135 is formed from multiple levels and metal layers ofthe BEOL build-up structure. Such a multiple level structure isadditionally illustrated in the schematic side view illustrations ofFIGS. 4B-4C taken along sections B and C of FIG. 4A, respectively. Byway of example, FIGS. 4B-4C illustrate a BEOL build-up structureincluding four metal layers 132A-132D connected by four verticalinterconnect (e.g. via) layers 132A-132D. The metallic seal 122 isillustrated by light shading, while the die routing 135 is illustratedby darker shading. In an embodiment, the die routing 135 enters themetallic seal 122 in a lower metal level (e.g. 134C) and exits themetallic seal 122 (toward the die edge) in an upper metal level (e.g.134D) that is above the lower metal level. Also shown in FIGS. 4A-4C, inan embodiment, the metal layer in the lower metal level may have a finerline width, thickness, spacing, pitch, etc. compared to the metal layerin the upper metal level. Alternatively, the die routing may enter themetallic seal 122 in the upper metal level that is above the lower metallevel, and exit the metallic seal 122 in the lower metal level.

Referring now to FIG. 4D, additional barriers may be included to provideadditional protection, for example to moisture diffusion. In someapplications it may be worthwhile to provide additional passivation toensure process design compliance standards are met. This can beparticularly pertinent to low dielectric constant (low-k) materials usedwith the finer and lower metal layers. For example, this may be due tothe ability to moisture to diffuse through materials in the build-upstructure, and low-k materials in particular. In the embodimentillustrated in FIG. 4D, the adjacent die 104 or stitched die structures100 are partially scribed, followed by a conformal deposition of one ormore barrier layers 412, 414. Exemplary barrier layers include, but arenot limited to, inorganic materials such as oxides (e.g. SiO₂, Al₂O₃,etc.) and nitrides (e.g. silicon nitride, etc.). In an embodiment, theone or more barrier layers 412, 414 are deposited using a conformaldeposition technique such as, chemical vapor deposition, physical vapordeposition (with incremental step coverage such as with ion/plasmaenergy assist, and source to trench angle management) etc. The one ormore barrier layers may have a substantially uniform thickness spanningalong build-up structure diced edge 121 (e.g. sidewalls) that issubstantially orthogonal to the metal layers (e.g. M_high, M_mid, M_low,etc.). Following deposition of the one or more barrier layers 412, 412,the one or more barrier layers may be patterned to expose chip contactpads at the upper metallization layers, followed by dicing throughsemiconductor substrate 101 to form discrete die 104 or stitched diestructures 100.

FIG. 5 is a schematic illustration of a portion of die-to-die routing130 including stitch routing 136 connected to die routing 135 thatextends through a metallic seal 122 accordance with an embodiment. FIG.5 differs from FIGS. 3 and 4A, with the addition of stitch routing 136and fan out region 137. In one embodiment, the die routing 135 exitingthe metallic seal 122 may include a fan out region 137 where the routingline pitch or spacing is increased. This may facilitate the alignment ofstitch routing 136 with a coarser line width, spacing, or pitch comparedto the metal layer 134 used to form die routing 135. Fan out routing 137may additionally facilitate routing through the metallic seal 122 at afiner pitch (chip like pitch) compared to the stitch routing 136. Thismay reduce the gap, or opening 124, in the metallic seal 122 and reduceexposure. Thus, the die routing 135 may navigate through the metallicseal 122 using chip-like design rules to minimize the gap, or opening124, in the metallic seal 122, and then widen to manufacturingrequirements for stitching. In an embodiment, where fan out region 137is not present, stitch routing 136 may still include coarser line width,with reduced spacing, where line pitch remains the same. Stitch routing136 may have the same thickness as the metal layer 134, for example touse the standard dielectric layer for the particular level within theBEOL build-up structure.

By way of example, in an embodiment stitch routing 136 may have a pitchof 1 μm (0.5 μm line width, μm line spacing). This may correspond to awiring density of 1,000 wires/mm/layer. In such an example, the on-chipdesign rule for that BEOL layer may be 0.2 μm pitch (0.1 μm line width),which may correspond to a wiring density of 5,000 wire/mm/layer. Thus, 1mm of beachfront in the stitching area may accommodate 1,000 wires,while the metallic seal 122 opening 124 may have a reduced size such as0.2 mm. The remaining 0.8 mm can be full seal area, allowing for greaterseal coverage.

Referring now to FIGS. 6A-6B the die-to-die input/output circuits 108Amay optionally include protection circuits 600 in accordance withembodiments. The protection circuits 600 may mitigate leakage orcharging along die routings 135. For example, the protection circuits600 may mitigate charging along the die routings 135 due to dicing (e.g.saw, laser, plasma), debonding, etc. The protection circuits 600 mayalso disable unconnected/diced dies 104 and mitigate leakage ofunconnected die routings 135. FIG. 6A is a circuit diagram for twoconnected dies in accordance with an embodiment. FIG. 6B is a circuitdiagram for two diced dies in accordance with an embodiment.

In accordance with embodiments, a stitched die structure 100 may includea semiconductor substrate 101 including a first die area 110A of a firstdie 104A and a second die area 110B of a second die 104B separate fromthe first die area 110A, as illustrated in FIG. 1. As shown in FIGS.3-5, the first die area 110A includes a first core logic circuit region108B and a first die-to-die input/output circuit region 108A, and thesecond die area 110B includes a second core logic circuit region 108Band a second die-to-die input/output circuit region 108A. The BEOLbuild-up structure 120 spans over the first die area 110A and the seconddie area 110B, the BEOL build-up structure 120 includes a die-to-dierouting 130 to electrically connect the first die-to die input/outputcircuit region 108A to the second die-to-die input/output circuit region108A. The die-to-die routing 130 may include a first die routing 135, asecond die routing 135, and a stitch routing 136 physically connectingthe first die routing 135 to the second die routing 135. The stitchrouting 136 may have a wider line width than the first and second dieroutings 135. The stitch routing 136 may additionally have a coarserline pitch than the first and second die routings 135. Further, thestitching may include the higher, middle and/or lower metal layers basedon requirements (e.g. wiring, shoreline available), and cost tradeoffs(e.g. extra lithography costs, extra passivation if M_mid or M_low areused).

Referring now specifically to FIGS. 6A-6B, the first die-to-dieinput/output circuit region 108A in includes a driver 610, and thesecond die-to-die input/output circuit region 108A includes a receiver640. The die routings 135 of the first die area 110 are connected to adriver 610 output on one side of the dicing area 150, and die routings135 of the second die area 110 are connected to a receiver 640 input onan opposite side of the dicing area 150 in a driver-receiverconfiguration. When the adjacent die areas 110 are connected (e.g. withstitch routing 136), the power switch 612 and high impedance buffer 614inputs to the driver 610 are enabled, so the buffer is capable ofdriving signals. Likewise, the power switch input 642 and enable/disableinput 644 to the receiver 640 are enabled. When the adjacent die aredisconnected (e.g. scribed), the power switch input 612 and highimpedance buffer enable/disable input 614 to the driver 610 aredisabled. Likewise, the power switch input 642 and enable/disable input644 to the receiver 640 are disabled (driver tristated). In alternativeembodiments, thick oxide devices, or a cascading device can beimplemented to add robustness to the interface. The figure shows auni-directional link for simplicity, but a bi-directional link is alsofeasible.

The protection circuits 600 illustrated in FIGS. 6A-6B are optional, andembodiments are not limited to those particular configurationsillustrated. As shown, the protection circuits 600 may include one ormore antenna diodes 602, 604 or other suitable structure, such as agrounded gate device (core or thick oxide), etc. Antenna diodes asdescribed herein are small diodes, for handling process level charging,and very small electrostatic discharge (ESD) events. These may be muchsmaller than (formal or regular IO) ESD protection circuits. Inaccordance with some embodiments, the driver 610 and receiver 640 may beformed with thick oxide devices, and protection circuits 600 are notincluded. In accordance with embodiments, one or more protectioncircuits 600 may be included to protect the dies when they are dicedapart. In a first configuration, only a single antenna diode 602 ispresent adjacent the receiver 640 side (with no protection circuit onthe driver 610 side). In an embodiment, antenna diode 602 is coupled toground or low voltage source (e.g. Vss). In a second configuration, aplurality of antenna diodes 602, 604 are present adjacent the receiver640 side (with no protection circuit on the driver 610 side). In anembodiment, antenna diode 604 is coupled to a high voltage or powersource (e.g. Vdd). In a third configuration one or more antenna diodes602, 604 are coupled to the receiver 640 side and an antenna diode 602is coupled to the driver 610 side. In a fourth configuration, one ormore antenna diodes 602, 604 are coupled to the receiver 640 side and aplurality of antenna diodes 602, 604 are coupled to the driver 610 side.

In a specific embodiment, the second die-to-die input/output circuitregion 108A (right) includes an antenna diode 602 coupled to the seconddie-to-die routing 135 between the receiver 640 and the stitch routing136. In an embodiment, the first die-to-die input/output circuit region180A (left) comprises a second antenna diode 602 coupled to the firstdie-to-die routing 135 between the driver 610 and the stitch routing136. In an embodiment, the first die area 110 (left) includes a thirddie-to-die input/output circuit region 108A including a second receiver640 opposite the first core logic circuit region from the firstdie-to-die input/output circuit region 110, and the receiver 640 iscoupled with a third die routing 135 that terminates near a diced edge121 of the stitched die structure 100. For example, one or more antennadiodes 602, 604 may be coupled to the third die routing 135 between thereceiver 640 and the terminal end of the third die routing 135 near thediced edge 121 of the stitched die structure 100. Such a structure is atleast partially illustrated in FIG. 6B (right) as combined with FIG. 6A(left).

In accordance with embodiments, the die-to-die input/output circuits108A may optionally include a hardware based detection circuit inaccordance with embodiments. For example, a detection circuit may becoupled to the receiver 640 and another die routing to detect presence(or absence) of the first die, or alternatively coupled to the driver610 and a another die routing to detect presence (or absence) of thesecond die. FIG. 7A is a detection circuit diagram for a connected dieroutings accordance with an embodiment. FIG. 7B is a detection circuitdiagram for unconnected die routings in accordance with an embodiment.As shown, the detection circuit 700 may include a pullup 710 connectedto a die routing 135 between the die area 110 edge and a receiver 650.The receiver 650 output is then provided to a logic 720, which is thendirected to the enable inputs 612, 614, 642, or 644, each withappropriate timing and polarity. Additionally, software controls 722(such as power states, repair, etc.) are input to the logic 720. Adetect signal from the detection circuit 700 may be utilized to setother configuration properties such as the power switch and inputenable/disable to the driver 610 or receiver 640. For example, inapplication if the receiver 650 senses a low detect signal, then theadjacent die is present. If the receiver senses a high detect signal,then an adjacent die is absent, not connected. The particular embodimentillustrated in FIG. 7A is one implementation for how connected dies canbe detected in hardware on a system on chip. In operation, a signalcould be sent from a die on one side, and checked in a die on the otherside to establish presence etc. Other alternatives are envisioned inaccordance with embodiments, such as a fused bit, or board or packagestrapping.

Referring now to FIG. 8A a schematic top view illustration is providedof a wafer 102 including an array of die areas 110 in accordance with anembodiment in which a metallic seal 122 is formed around adjacent die104 and die areas 110 that are interconnected with die-to-die routing130. Similar to the discussion with regard to FIG. 2A, as shown in theclose-up illustration in FIG. 8A, the die-to-die routing 130additionally includes stitch routing 136 that physically andelectrically connects the first and second die routings 135 of adjacentdie. The die routing 135 and stitch routing 136 with regard to FIG. 8Amay be formed similarly as those described above with regard to FIGS.1-5, with omission of extending through a metallic seal 122. Onedifference compared to FIG. 2A, is that metallic seals 122 areselectively formed outside of the peripheries of the die areas 110.Thus, the metallic seals 122 in the embodiment illustrated in FIG. 8Aare not pre-formed with the reticles used to form die areas 110.Instead, the metallic seals 122 may be formed after formation of theBEOL build-up structure 120, after dicing, or using the stitching toolused to form stitch routing 136 concurrent with formation of the BEOLbuild-up structure 120. In accordance with the embodiment illustrated inFIG. 8A, die routing 135 may be still be pre-formed with the reticlesused to form die areas 110. Likewise, active areas 108 includingdie-to-die input/output circuits 108A and core logic circuits 108B maybe similarly formed.

In an embodiment, the formation die-to-die routing 130 and selection ofscribe/dicing areas is customized around each die 104. While theexemplary stitched die structure 100 illustrated in FIG. 8A includes twodie 104 (illustrated by die areas 110) examples, embodiments are notlimited and any number of die 104 may be included, such as three, four,etc. and may be stitched together at different sides. For example, dierouting 135 may be pre-formed and stitch routing 136 may be selectivelyformed at any or all sides of the die areas 110 to allow for theformation of die-to-die routing 130 between any adjacent die 104. In anembodiment, die routing may also be selectively formed.

Referring now to FIG. 8B, a flow chart is provided of a method offorming a stitched die structure 100 with a custom metallic seal inaccordance with embodiments. At operation 8010 the BEOL build-upstructure 120 is partially formed. That is, a significant portion of themetal routing is formed, yet processing has not continued to the pointof fabricating the bond pads. At this stage processing of the metalrouting has not yet reached the point for conventional wafer testingmethods. At operation 9020 die clusters are binned (e.g. identified asgood or bad) based on process data. For example, the process data may bebased on early electrical test data from front-end-of-the-line (FEOL)and/or early BEOL fabrication stages, optical test data, and yieldtrends for wafer die location. Data may include electrical test oroptical inspection data. For example electrical test data may includeprobed (touch) tests to determine electrical quality of transistors orinterconnects, simple circuits (e.g. ring oscillator or the like).Probed touchdown testing may be accompanied by a subsequent clean/repairoperations. An exemplary configuration is illustrated and described inmore detail with regard to FIG. 9. No-touch testing may also be utilizedto bin the dies. Exemplary no-touch testing methods include opticalinspection, and systematic (e.g. wafer maps) and historical trends, andproject yield to identify the die sets. No-touch testing may includeradio frequency, or optical probes, or probing on a remote area withtest signals propagated to DUT (as in FIG. 9). Based on thisinformation, the formation of the BEOL build-up structure 120 iscompleted at operation 8030 to include die-to-die routing 130 betweenspecified die sets. Dies 104 within bad clusters may not beinterconnected. In some embodiments, metallic seals 122 are only formedaround the specified die sets that will become the stitched diestructures 100 at operation 8040. In this manner, the uncommitted layersof the BEOL structure can then be used to form the custom seal rings,routings, and die sets. Additionally, custom routing 1125 patterns toinput/output circuits 1010 can be fabricated, as discussed in moredetail with regard to FIGS. 10-11B. In an embodiment, metallic seals 122are formed after formation of the BEOL build-up structure 120. This mayinclude a pre-dicing operation to expose diced edges 121 of the BEOLbuild-up structure 120 of the stitched die structures 100. The stitcheddie structures 100 are then scribed at operation 8050.

While the embodiments illustrated and described with regard to FIGS.2A-2D and 8A-8B are described and illustrated separately, some aspect ofthese description may be combined. For example, the process data reliedupon in the discussion of FIGS. 8A-8B to bin the dies 104 into differentclusters can also be utilized in the process sequence described withregard to FIGS. 2A-2D. In this manner, stitch routing 136 may be moreselectively formed. In such a circumstance, dicing associated with FIGS.2A-2D may not be accompanied by cutting through a die-to-die routing130.

In accordance with some embodiments, and particularly those includingcustom die-to-die routing, seal rings, and scribes, determining the diequality may be best guessed, with a hard test not being performed priorto committing to die sets. In some embodiments, the die areas 110 may betested prior to forming the BEOL build-up structure 120 and/or earlyBEOL build-up structure 120 stages, followed by a determination of die104 sets. FIG. 9 is a schematic top view illustration of a probingarrangement on a wafer 102 supporting an array of dies in accordancewith an embodiment. In such a configuration probing may require a touchin a probe area 910, followed by a low-cost clean. The probe area 910may include a plurality of pins (or pads) 911 connected to various linessuch as power or ground lines 912, clock lines 914, and test lines 916.Test lines 916 may optionally be connected to a series of aggregators,repeaters, multiplexers 920 to allow a plurality of die areas 110 to betested in parallel. As shown, each die area 110 may additionally includea plurality of logic blocks 930-1, 930-2, etc. Such a test structure maybe fabricated on a partially formed BEOL build-up structure 120.

Fabrication of a custom seal ring 122, such as with the embodimentdescribed with regard to FIGS. 8A-8B, can additionally facilitate theability to reconfigure a custom I/O connections for the dies 104 or diesets 100. FIG. 10 is a schematic illustration of a die 104 or die set100 input/output circuits 1010 including digital components 1012 andanalog components 1014 in accordance with an embodiment. As shown thedigital I/O components 1012 and analog I/O components 1014 work togetherto make an I/O circuit 1010. Each die 104 or die set 100 may include aplurality of I/O circuits 1010 (e.g. 1010-1, 1010-2 . . . 1010-n). Thedigital components 1012 may provide control and status, while the analogcomponents 1014 may provide the actual driver and receive, and signalconditioning. In accordance with embodiments, if a manufacturer iscustom designing the seal ring 122 and die-to-die routing 130 thenadditional re-programming options are available for the I/O connectionsto the I/O circuits 1010. For example, this may be accomplished with adirect-write (e.g. laser write, e-beam write) to customize wiring, andmay be done at the coarsest lithography levels (though not required),just prior to formation of the I/O connections. Ordinarily I/Oconnection 1120 (e.g. pin, pad) layout is fixed based on chip/packagetype (e.g. dynamic random-access memory (DRAM), peripheral componentinterconnect express (PCIE), etc). FIG. 11A is a schematic illustrationof a die I/O connection 1120 configuration with an unused spare I/Ocircuit 1010-S in accordance with an embodiment. FIG. 11B is a schematicillustration of a die I/O connection 1120 configuration with a connectedspare I/O circuit 1010-S in accordance with an embodiment. In theembodiment illustrated in FIG. 11A, the I/O routings 1125 and/or I/Oconnections 1120 are routed to the plurality of I/O circuits 1010 (e.g.1010-1, 1010-2 . . . 1010-n, and not routed to the spare I/O circuit1010-S. In the embodiment illustrated in FIG. 11B, the I/O routings 1125and/or I/O connections 1120 are re-routed to skip a bad I/O circuit1010-X (or corresponding circuit connected to the bad I/O circuit) andto also connect to the spare I/O circuit 1010-S. In accordance with anembodiment, re-routing can be implemented during the same operation(s)as forming the customized seal ring 122.

In the exemplary embodiments illustrated in FIGS. 11A-11B, a pluralityof input/output circuits 1010 and a plurality of die I/O connections1120 are coupled to the plurality of I/O circuits 1010 with a pluralityof routings 1125. Additionally, one or more I/O circuits 1010 (e.g.1010-S, 1010-X) are not coupled to a die I/O connection 1120. In anembodiment, a spare I/O circuit 101-S or bad I/O circuit 1010-X locatedat an end of a series of I/O circuits 1010, or within the series is notcoupled. Additionally, this may or may not change the routing 1125patterns. In an embodiment, there is a first group of the plurality ofroutings with a first characteristic routing pattern (e.g. top routingsin FIG. 11B above bad I/O circuit 1010-X), and a second group of theplurality of routings with a second characteristic routing pattern (e.g.bottom routings in FIG. 11B below bad I/O circuit 1010-X). A differencein the first characteristic routing pattern and the secondcharacteristic routing pattern is correlated with the input/outputcircuit (e.g. 1010-X, or 1010-S) not being coupled to a die input/outputconnection 1120. For example, the resultant wiring configuration may beadopted as the result of tests or other means for analyzing theunderlying I/O circuits 1010 and/or processing as described with regardto a customized approach.

Referring now to FIG. 12A a schematic top view illustration of a module1200 (e.g. package) including a stitched die structure 100 in accordancewith an embodiment. As shown, the module 1200 may include a stitched diestructure 100 mounted on a module substrate 1202, optionally with anyother chips 1210. The stitched die structure 100 and optional chip 1210may be encapsulated within a hermetic seal 1204, which may addadditional physical and electrical protection. In accordance withembodiments, the metallic seals 122 within the stitched die structure100 may provide an added layer of protection for high reliabilitysystems, or alternatively, facilitate relaxing some of the on-chip sealand/or keep out zone requirements for cost-sensitive systems or lowreliability systems.

FIGS. 12B-12C are schematic top view illustrations stitched diestructures 100 for high reliability systems including multiple metallicseals 122 around active areas 108 in accordance with embodiments. Asshown multiple seal rings 122 may be provided for additional protection,and larger keep out zone from the active area 108 to the edge of the diearea. Specifically, FIG. 12B is an illustration of a stitched diestructure 100 including multiple custom metallic seals 122 formed aroundmultiple die in accordance with an embodiment. FIG. 12C is anillustration of a stitched die structure 100 including multiplepre-formed metallic seals 122 around each die in accordance with anembodiment.

FIGS. 12D-12E are schematic top view illustrations stitched diestructures 100 for cost-sensitive or low reliability systems inaccordance with embodiments. As shown, the number of metallic seals 122can be reduced, or even eliminated. Additionally, the keep out zone fromthe active area 108 to edge of the die area can be reduced.Specifically, FIG. 12D is an illustration of a stitched die structure100 including a custom metallic seal 122 formed around multiple die inaccordance with an embodiment. FIG. 12E is an illustration of a stitcheddie structure 100 including a pre-formed metallic seal 122 around eachdie in accordance with an embodiment.

In utilizing the various aspects of the embodiments, it would becomeapparent to one skilled in the art that combinations or variations ofthe above embodiments are possible for forming stitched die structures.Although the embodiments have been described in language specific tostructural features and/or methodological acts, it is to be understoodthat the appended claims are not necessarily limited to the specificfeatures or acts described. The specific features and acts disclosed areinstead to be understood as embodiments of the claims useful forillustration.

What is claimed is:
 1. A multi-die structure including: a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area separate from the first FEOL die area; wherein the first FEOL die area includes a first die-to-die input/output circuit region, and the second FEOL die area includes a second die-to-die input/output circuit region; a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area, the BEOL build-up structure comprising a die-to-die routing to electrically connect the first die-to die input/output circuit region to the second die-to-die input/output circuit region.
 2. The multi-die structure of claim 1, wherein the first FEOL die area includes a first core logic circuit region, and the second FEOL die area includes a second core logic circuit region.
 3. The multi-die structure of claim 1, wherein the die-to-die routing includes a first die routing, a second die routing, and a stitch routing physically connecting the first die routing to the second die routing.
 4. The multi-die structure of claim 3, wherein the stitch routing has a wider line width than the first die routing and the second die routing, and the stitch routing has a coarser line pitch than the first die routing and the second die routing.
 5. The multi-die structure of claim 1, wherein the BEOL build-up structure further comprises: a first metallic seal directly over a first peripheral area of the first FEOL die area; a second metallic seal directly over a second peripheral area of the second FEOL die area; and the die-to-die routing extends through a first opening in the first metallic seal and a second opening in the second metallic seal to electrically connect the first die to the second die.
 6. The multi-die structure of claim 5, wherein the die-to-die routing enters the first metallic seal in a lower metal level in the BEOL build-up structure and exits the first metallic seal in an upper metal level in the BEOL build-up structure above the lower metal level.
 7. The multi-die structure of claim 5, wherein the first FEOL die area includes a third die-to-die input/output circuit region including third die routing that terminates near a diced edge of the multi-die structure.
 8. The multi-die structure of claim 5, further comprising one or more barrier layers including a substantially uniform thickness spanning along a diced edge of the multi-die structure substantially orthogonal to metal layers of the BEOL build-up structure.
 9. The multi-die structure of claim 1, further comprising a metallic seal around the first FEOL die area, the second FEOL die area, and the die-to-die routing.
 10. The multi-die structure of claim 1, wherein the first FEOL die area includes a third die-to-die input/output circuit region including third die routing that terminates near a diced edge of the multi-die structure.
 11. The multi-die structure of claim 10, further comprising a plurality of input/output connections coupled to the first die-to-die input/output circuit region and the second die-to-die input/output circuit region.
 12. The multi-die structure of claim 10, wherein the third die-to-die input/output circuit region is not coupled to a die input/output connection.
 13. The multi-die structure of claim 1, wherein the first die-to-die input/output circuit region in includes a driver, and the second die-to-die input/output circuit region includes a receiver.
 14. The multi-die structure of claim 13, wherein the die-to-die routing includes a first die routing and a second die routing, and the second die-to-die input/output circuit region comprises an antenna diode coupled to the second die routing between the receiver and the second die routing.
 15. The multi-die structure of claim 14, wherein the first die-to-die input/output circuit region comprises a second antenna diode coupled to the first die routing between the driver and the first die routing.
 16. The multi-die structure of claim 14, further comprising a detection circuit coupled to the receiver and a second die routing to detect presence of the first die.
 17. The multi-die structure of claim 13, further comprising a buffer enable/disable input to the driver, a first power switch input to the driver, an enable/disable input to the receiver, and a second power switch input to the receiver.
 18. The multi-die structure of claim 1, wherein the first die and the second die are different die types.
 19. The multi-die structure of claim 1, wherein the first die and the second die are a same die type.
 20. The multi-die structure of claim 19, wherein the same die type is selected from the group consisting of a graphics processing unit (GPU) and a central processing unit (CPU). 